1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and, more specifically, to a synchronous semiconductor memory device that can eliminate difference of data output timing in a burst read operation.
2. Description of the Background Art
In order to meet the demand for higher frequency operation of synchronous semiconductor memory devices, a double data rate SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory: hereinafter referred to as a DDR-SDRAM) has been developed and come to be practically used, in which data is communicated with the outside in synchronization with both rising and falling edges of an external clock signal.
As compared with an SDRAM that operates in synchronization with either the rising edge or the falling edge of the external clock signal, the DDR-SDRAM is capable of reading data and writing data approximately at the double rate.
It is noted, however, that the DDR-SRAM operates at a very high speed, and therefore, it is necessary to adjust data output timing with very high precision particularly in order to have the value of tLZ defining a timing period between the external clock signal and the first output data and the value of tAC defining the timing period between the external clock signal and the second and the following output data within specific tolerable ranges.
In view of the foregoing, a method has been proposed (hereinafter referred to as a conventional art), for example, in Japanese Patent Laying-Open No. 11-86547, for adjusting data output timing in a synchronous semiconductor memory device, though not in a DDR-SDRAM.
Generally, in a burst read operation in a synchronous semiconductor memory device such as a DDR-SDRAM or an SDRAM, the time period until the first data is output corresponds to the time period necessary for the voltage level to change from the precharge level (Vcc/2). In contrast, the time period until the second or the following data is output corresponds to the time period necessary for the voltage level to change form the power supply voltage Vcc or from the ground voltage GND. Therefore, it follows that the first data output timing becomes relatively faster than the second or the following data output timing.
The above described conventional art is for adjusting data output timing in an SDRAM. It does not disclose, however, any measure to eliminate the difference between the first data output timing and the second or the following data output timing in a burst read operation.
In a burst read operation in a synchronous semiconductor memory device, if all the data output timings were the same, prescribed set-up time and prescribed hold time for the clock signal to take data would be constant.
Therefore, even when there is a variation in electrical characteristics of circuits for externally outputting data (hereinafter also referred to as data output circuits) provided in mass-produced synchronous semiconductor memory devices and the set-up time and the hold time come to have some error as a result, it is highly possible that a data reading apparatus can read the data output from the synchronous semiconductor devices.
When there is a variation in electrical characteristics of the data output circuits provided in mass-produced synchronous semiconductor memory devices with the data output timing being different, it would be more difficult to ensure the prescribed set-up time and the prescribed hold time to properly receive data signals. Therefore, there would be a higher possibility of failure of proper data reading by the data reading apparatus. Conventionally, such product has been in many cases regarded as a defective device, resulting in lower production yield.